Jim Lawson
Jim Lawson
Chisel should issue a warning for modules with no connected ports. Prompted by issue #545.
Should the interpreter create it's own lowering compiler that does not call the firrtl.CheckCombLoops transform so it can allow combinational loops as it did before?
Import `CC`, `CXX`, `CCFLAGS`, `CXXFLAGS`, `CPPFLAGS`, `LDFLAGS` and incorporate them in the flags used to build C++ simulations. Although similar effects can be achieved via the `--more-vcs-flags`, and `--more-vcs-c-flags` command...
In order to run Synopsis `vcs` with newer versions of `gcc`, we need to be able to add some flags to the command line. Since this is dependent on the...
(from @seldridge freechipsproject/firrtl#916) freechipsproject/chisel-testers#214 makes sense, generally. The user should be able to add options. However, I think there's motivation for verilogToCpp or verilogToVerilator to choose specific options based on...
PeekPokeTester catches TestApplicationException, returning failure if the exit code is non-zero. Some simulations (notably vcs) do not set a reliable exit code, but in any case, we should signal up-level...
The various backends share quite a bit of common code. It would be good to refactor this before they diverge.
Currently, chisel-testers uses implementation details to interrogate the DUT graph. We need to provide a suitable API in chisel3. See ucb-bar/chisel3#231
### Contributor Checklist - [ ] Did you add Scaladoc to every public function/method? - [ ] Did you update the FIRRTL spec to include every new feature/behavior? - [...