Genadi V. Zawidowski
Genadi V. Zawidowski
ULONG_MAX in both places need to replace with UINT32_MAX
I can not now prepare fine-indented code for creating PR... Archives can be used for generate diffs... My last activity arount CMSIS Cortex-A interrupt handling memorized as too hard quest...
Proposed fix [patch.zip](https://github.com/ARM-software/CMSIS_5/files/10981364/patch.zip)
You right. CPUECTLR bs a Cortex-A53 specific register (like different-specs ACTLR for Cortex-A7 and Cortex-A9. Mentioned document is `DDI0500J_cortex_a53_r0p4_trm.pdf` All these updates tested on Allwinner A64. May be right paramerer...
For reference, predefined sybols fo _gcc_ with _-mcpu=cortex-a53_ in attachments. [defines_aarch64.txt](https://github.com/ARM-software/CMSIS_5/files/10762362/defines_aarch64.txt) [defines_aarch32.txt](https://github.com/ARM-software/CMSIS_5/files/10762363/defines_aarch32.txt)
all okay
Проект: http://www.cqham.ru/forum/showthread.php?38177-%C0%E8%F1%F2-2&p=1918115&viewfull=1#post1918115 Схема: [mainunit_sch.pdf](https://github.com/ua1arn/hftrx/files/11295275/mainunit_sch.pdf)
All commits from previously opened pull request
I can confirm - remap in style 0 succesfully work. Init params also updated.
Other compilers may have different predefined macro.