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                                            tyoungsc

DPC++FPGA DB example: dataset for FPGA target is not included

The files are intentionally not included since they are over 1GB in size and would really bloat the repo. From the [DB README](https://github.com/oneapi-src/oneAPI-samples/tree/master/DirectProgramming/DPC%2B%2BFPGA/ReferenceDesigns/db): > In the data/ directory, you will...

DPC++FPGA DB example: dataset for FPGA target is not included

@mdbtucker what do you think about my alternative approach? I don't think adding these files to the repo is acceptable; but writing a data generator in C++ is reasonable, but...

DPC++FPGA DB example: dataset for FPGA target is not included

@yuguen-intel FYI. I removed the bug label in favour of enhancement.

[SYCL][FPGA] Expose value_type and min_capacity from sycl::ext::intel::experimental::pipe

> @tyoungsc I copied the changes to the specification and the implementation verbatim from your commit [e1619fa](https://github.com/intel/llvm/commit/e1619fa64616a05ae962952b7bc6517af9f74dda), but noticed that the type of `min_capacity` is `size_t` in the specification while...

[SYCL][FPGA] Expose value_type and min_capacity from sycl::ext::intel::experimental::pipe

> Needless to say, the spec and the implementation should agree. I see that you also use `size_t` for the `map` and `unmap` member functions of the host pipe class....