tristanitschner
tristanitschner
Example: ```vhdl entity incorrect_choice_length is end entity; architecture arch of incorrect_choice_length is type some_datastructure_t is record name : string; value : natural range 0 to 3; end record; type some_datastructure_array...
I'm trying to implement a generic CRC package. Unfortunately GHDL doesn't support exporting an entity that makes use of such a package as Verilog code, which I'd really like do...
**Description** So recently I have been trying to work around the fact, that the maximum integer size in VHDL is 2^32 - 1. Given the amount of ram available nowadays,...
This VHDL file with valid syntax (according to the standard): ```vhd :file: reverse.vhd library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all; entity reverse is port ( clk : in std_logic; a :...
**Note**: This is not an issue, but merely a notice to Mr. ZipCPU. Since I am certain from reading his blog that he is a very busy man indeed, I...
This adds support for the * graphics/framebuffers * graphics/pong examples for the ULX3S board. Has been tested on my board.
Hi there, I'm using your CPU in a quad core constellation on a nexys video. The SoC was generated with: ``` python3 -m litex_boards.targets.digilent_nexys_video --cpu-type=naxriscv --bus-standard axi-lite \ --with-video-framebuffer --with-coherent-dma...