axi4 topic
chisel3-axi
Chisel3 AXI4-{Lite, Full, Stream} Definitions
axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Cores-VeeR-EH1
VeeR EH1 core
Cores-VeeR-EL2
VeeR EL2 Core
FPGA-Application-Development-and-Simulation
《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).
core_ft60x_axi
FTDI FT600 SuperSpeed USB3.0 to AXI bus master
ravenoc
RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
tnoc
Network on Chip Implementation written in SytemVerilog
axi4-interface
AXI4 and AXI4-Lite interface definitions