Tobias Jensen
Tobias Jensen
Great, i'll get to work on the language translation
As this is starting to look stale i just wanted to document that i am in fact still active and working
I'd like to add Danish as a language
Making a plugin for micro that adds LSP support *should* be possible, however it should certainly be possible, albeit a better autocompletion integration might be needed
Looks like old commit already merged got in this pull request too, not sure how to fix.
This PR seems to fix the last issue apart from the makefile, however I am having a bit of trouble compiling on windows with the oss-cad-suite as the verilator runtime...
My guess is this is a bug in the interaction of chisel and firtool, however I have not been able to find any code that could generate the files wrong
The interesting part here is there seems to be no issues when using chisel.stage.emitSystemVerilog and manually adding layers