threewholefish

I'm interested in generating parsers/generators in Verilog/SystemVerilog, which would be used as one endpoint with the existing C/C++ implementations as the other. I've used [Jinja](https://jinja.palletsprojects.com/en/3.1.x/) for code generation in previous...

Further to this, I think that any information in an `INFO` line should be short and sweet, and the full details of the frame reserved for `DEBUG`. IMO, RX and...

An example of padding within the composite is the following from the [CME MDP3 spec](https://github.com/real-logic/simple-binary-encoding/blob/master/sbe-tool/src/test/resources/FixBinary.xml): ```xml ``` `numInGroup` has an offset of 7, meaning there are 5 implied padding bytes...

Take this set from the [CME MDP3 spec](https://github.com/real-logic/simple-binary-encoding/blob/master/sbe-tool/src/test/resources/FixBinary.xml): ```xml 0 1 2 3 4 5 6 7 ``` The raw value `0x1` should correspond to a decoded value of `["LastTradeMsg"]`,...