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                                            David Thornley

Set CAS_LATENCY/GATE_OPEN_LATENCY to (2*CL)+1 for AR933x running DDR2

Documented in https://github.com/pepe2k/u-boot_mod/commit/3527b8cc2a989e51197831eab1f941429f8ffeea Unstable behaviour in openwrt/lede found with use of SKW72 (Skylabs) OEM AP121 reference board: - AR9331-AL3A, Flash = Winbond (25Q128FVSG) Ram = Zentel DDR2 (A3R12E40CBF). Prior to...