Thomas Johnson

[feature request] Option to use SystemVerilog unpacked arrays for `Vec`s in IO ports

4

Although SpinalHDL `Vec`s work well for interfacing between SpinalHDL components, they produce a bunch of named ports in Verilog modules, which can make it really tedious to interoperate with existing...

Observations about AFix

3

I'm currently working on a project involving a lot of fixed-point math, and I noticed a few things that annoyed me about the `AFix` API that I wanted to share....

Fix FSM bug

4

Closes #1528 # Context, Motivation & Description See issue for details. # Impact on code generation `StateFsm` and `StateParallelFsm` now generate `onEntry` statements duplicating the `onEntry` blocks of the entry...

Outer FSM `whenIsActive` statements always win vs. nested FSM `onEntry` statements for combinational logic

2

If an FSM drives a combinational signal from the `whenIsActive` block of one of its states, and then transitions to a nested FSM state whose entry state has an `onEntry`...

Change AFix division

4

# Context, Motivation & Description The `AFix` `/` operator appears to have not been changed since the original implementation of `AFix`, and I'm skeptical that it was ever used --...

[feature request] Some way to share constants between Spinal and Verilog/VHDL

3

Right now my team is working on projects that have both Verilog and SpinalHDL components. We have a lot of hardware-dependent constants, so we end up with Verilog headers that...

Related to ideas in #1476 # Context, Motivation & Description Sometimes a function will have a `RoundType` argument that decides how rounding is done, but you want to make sure...