TCal
At the VexRiscv commit used by pythondata-cpu-vexriscv to build the verilogs, there is a clash in the use of CSR 0xBC0, used both by CfuPlugin for its state/index/enable register, and...
The user should know when their implementation does not meet their stated timing goal. It is not clear from vpr when this is the case. #### Proposed Behaviour Perhaps by...
Tested on Arty and Icebreaker. Sample usage from the BaseSoC for Arty, to output the analog signal on the first pin of PMOD B: ``` def add_dac(self): self.platform.add_extension(arty.raw_pmod_io("pmodb")) outsig =...
Currently the build template for using SymbiFlow does not check whether timing is met. It should. The `Makefile` that's generated sends the output from `symbiflow_route` (and each other step) to...
See https://github.com/im-tomu/fomu-workshop/pull/410/checks?check_run_id=1616270863#step:10:5267. `add_dfu_suffix` has been removed from the latest litex_boards.
Keyword Spotting doesn't fit on Fomu with current Yosys due to memory R/W check (but there's a fix)
After the recent dependency bump (#619), I thought that it caused the KWS project to no longer fit on Fomu (over the limit by ~80 LCs). But then I was...
Use Conda if you need Yosys. Signed-off-by: Tim Callahan
When bumping VexRiscv and pre-generated verilog to recent master, we saw hangs using the CFU using either locally generated verilog files, or those generated upstream. Original discussion here: https://github.com/google/CFU-Playground/pull/592#issuecomment-1136534363. @davidlattimore...
The downloads page that the doc points to no longer exists. https://cfu-playground.readthedocs.io/en/latest/vivado-install.html points to https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/2020-1.html
Generate files `critpath.png` and `critpath.log` in the build `gateware/` directory. The PNG file contains a color-coded plot of placement color coded by LiteX, CPU, and CFU; the plot is overlayed...