Julien FAUCHER

This should be OK (clang-format was ran and tests were performed on a testcase). I have not run the integrated tests because I didn't found a way to only run...

Thanks, I understood the "reject" pattern thing. This should be ok. however I need to add tests for "for" constructions

I erm... third (?) this ! It is useful to have a ```systemverilog module_a_top( .signal_a (wire_signal_a ), .long_signal_b (wire_long_signal_b) ) ``` output since it allows an easy square selection of...

Bumping a bit on this one. This is the way SublimeText systemverilog does it and is quite neat when you have to add comments to describe the ports. Also, It...

Hi there, I got exactly on the same situation and the best I could get was this : ```json { "signal": [ {"name": "\\symb{csn}", "wave": "10.." }, {"name": "\\symb{clk}", "wave":...

As someone who just had the issue, one can work around this by using the cmake option ``` -DPYTHON_EXECUTABLE=`which python3` ```

Out of curiosity, which modification should be required in order to implement this ? Wouldn't be possible to detect if a configuration file (I don't remember the exact name) is...

I'm coming back on this to add a small ping. I am currently working on 4 different projects at the same time on the same machine and the fact that...

Thanks for your feedback. My point is mainly to ensure that this feature is taken into account if it enter the scope of your refactoring 🙂 In my opinion, only...

> I know what is your point, but it's important to define the details. I need your feedback :) Please do not worry, i'd rather have an extensive discussion and...