Stevo

Running the following chisel code produces a Verilog syntax error. At a high level, this code just takes the output of some submodule (BiplexFFT) and computes the power. ``` Scala...

https://github.com/vproc/vicuna/blob/bda35112a983e9adb4ea8413b0afc2f0d91e7563/rtl/vproc_top.sv#L221 If I issue a WFI instruction while Vicuna has outstanding work, even pending stores, then Ibex will go to sleep and gate its clock (see [here](https://github.com/michael-platzer/ibex/blob/c9e3fde2bbc2f1f5ef5ee8b47cb87746126e4f63/rtl/ibex_top.sv#L199)). But Vicuna will...

RAM_ASIC register file has multiply driven registers

2

https://github.com/vproc/vicuna/blob/38500cab0109c0d4afe51c2519ef0e85fe5b29b2/rtl/vproc_vregfile.sv#L161 If there are two write ports, and both try to write to the same address on the same cycle, how is this conflict resolved? The current implementation requires multiple...

CSR changes for Vector extension

1

The following CSR registers in the CPU probably need to be changed to properly flag having a vector extension. See the [privileged spec](https://riscv.org/technical/specifications/): 1. Machine ISA register, misa, bit 21...

https://github.com/vproc/vicuna/blob/bda35112a983e9adb4ea8413b0afc2f0d91e7563/rtl/vproc_cache.sv#L344 If a memory transaction error occurs, and the error is stored in the cache, all future cache hits to this address will return an error to the CPU. Neither...

verilator DUT cpp generation bug

1

Running a Verilator test twice doesn't reproduce the DUT cpp code. This can be seen by first generating a DUT with a Vec IO of some size, and then generating...

Support 2D dynamic array initialization

9

Example code (`temp.sv`): ``` function automatic void array_2d(); bit myarray [][]; myarray = new[3]; foreach (myarray[i]) myarray[i] = new[4]; endfunction ``` Command and error message: ``` $ verilator --lint-only temp.sv...

Allow for INT widths different from FP widths

1

Allows e.g. an FP16-only FPU to support INT8 and INT32: ``` localparam fpu_features_t CUSTOM = '{ Width: 32, EnableVectors: 1'b0, EnableNanBox: 1'b1, FpFmtMask: 5'b00100, IntFmtMask: 4'b1110 }; ```

## Required Information Example situation: Class: Alchemist Level: 10 Craftsmanship: 100 Control: 100 CP: 180 Recipe Name: Distilled Water Recipe Level: 1 Solver Seed: 1682791810261 ## Expected Behaviour First Basic...