stephanedr
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2
issues of
stephanedr
**Is this a similar or duplicate feature request?** - [ ] I don't know. I will go check it. - [x] No. **Is your feature request related to a problem?...
**Test case** ```systemverilog index = cond ? 0 : 1; port[cond ? 0 : 1]; ``` Without formatting options: **Actual output** ```systemverilog index = cond ? 0 : 1; //...
formatter