Bin Wu

Results 2 comments of Bin Wu

> This is only an issue if linking at the Verilog level. If there is another Chisel module named Queue, I believe that Chisel is smart enough to disambiguate them...

> Chisel 2 provided a `-moduleNamePrefix` to add a prefix to each Module name. This is one approach to "namespacing" that could solve this issue. For example, you could provide...