Srikrishna Iyer

Results 10 comments of Srikrishna Iyer

I would assume that any option set on the command line would override the 'default' set in the fusesoc.conf file if/when this is implemented.

This is to support DV usecase where a 'reusable' verification unit is contained within a SV package. In such a case, the tool (verilator, vcs etc) only needs a .f...

VCS already solves the problem of recompiling a package (and re-elaborate its partition) if a single file included in the package is changed. Compilation works at package granularity, not at...

To clarify, in the current setup, I don't even have to add *all* files to the .core file - I just need to pick one file at random from each...

Hi Olof, I was wondering if you were able to get to this yet. Thanks! Sri

Thank @olofk, we dont need it now (but we might in future).

Please see example: https://github.com/lowRISC/opentitan/blob/82278f92b83d280102116941dd1d6c19e6953bd8/hw/ip/rv_dm/dv/env/seq_lib/rv_dm_base_vseq.sv#L57 For `rv_dm` I defined 3 different reset strings with the same goal as yours - be able to apply different kinds of resets randomly and verify...

Looks like this was already reported over 2 years ago in #1149. Nevertheless, requesting renewed attention on this, hoping not too difficult to fix. Feel free to close bug on...

+1 for flexibility - it will be useful to enforce for example, ALL instances of some critical counter measure `foo` are properly verified, once we start extracting testplan bits from...

Will probably take the option 2 route.