sols1

discrepancy between Verilog and firrtl simulation

2

The code passes the test: ``` class RealGCDInput extends Bundle { val a = UInt(16.W) val b = UInt(16.W) } class RealGCD extends Module { val io = IO(new Bundle...

cat in initrd is necessary b/c of docker stats bug #https://github.com/docker/docker/issues/22882 docker says they have solution to this ugliness #https://github.com/docker/libnetwork/pull/1174 but it is not in 1.11.2