smokeflypaper

path to saves and chips: C:\Users\Your_User_Name\AppData\LocalLow\SebastianLague\Digital Logic Sim\V1\Projects\Your_Project_Name

> I think this is a duplicate of [#471](https://github.com/SebLague/Digital-Logic-Sim/issues/471), which you made. If this wasn't a duplicate, you should say so, to prevent confusion. no its not duplicate. Because Sebastian...

> > > I think this is a duplicate of [#471](https://github.com/SebLague/Digital-Logic-Sim/issues/471), which you made. If this wasn't a duplicate, you should say so, to prevent confusion. > > > >...

> [@smokeflypaper](https://github.com/smokeflypaper) This is actually invalid (see above) since it's not a issue with the simulation. It works just fine and does what is expected. Rather, it's your chips that...

> > What is sometimes happens for me is that, when J and K are up and I raise IN (clock) the circuit goes into a loop of alternation. Other...

> In the absence of any further word from Sebastian, it sounds like those of us who want the tree processed breadth-first have no other option than to fork the...

> > I tried upgrading the JK flip‑flop with those NAND gates in front. I also experimented with the steps‑per‑clock timing on a simple circuit (just one JK FF). My...

it looks that is the same issue i found here https://github.com/SebLague/Digital-Logic-Sim/issues/471#issue-3043739604