Sergei Andreev

Major bug/problem in the a22oi_1 standard cell

2

**⚠️ IMPORTANT** There is functional inconsistency between physical design/transistor-level schematic and Liberty/Verilog description of the a22oi_1 cell, if the cell is used in the design this will lead to a...

sky130.lylvs: XML parser error

1

## Root cause Angle brackets in copyright comment result in XML parser error: ``` > ... > # You should have received a copy of the GNU Affero General Public...

## Expected Behavior Pin labels in stdcells should be drawn on `Metal1.text` layer ## Actual Behavior Signal pin labels in `a221oi_1` cell are drawn on `Metal1.label` layer, PG pin labels...

Stdcell schematics must contain multiplier = 1

1

Layouts contain multi-fingered MOS devices, so CDL and SPICE netlists should be fixed to align with layout ## Expected Behavior ``` .SUBCKT sg13g2_inv_2 A VDD VSS Y *.PININFO A:I Y:O...

Missing Analog Pad cell from Liberty views

2

Analog pad cell should be characterized and included in Liberty views

Filler cells should be generated as empty subckts and provided in stdcells CDL and SPICE netlists

Updated: - MPW table - flow diagram - url path

change the output in the terminal window from: `Rule MIM.a: 0 error(s)` to `MIM.a: 0`