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                                            Shashi B

Is there a way to mix SystemVerilog UVM and UVM-Python environments?

The issue is that we use SV UVM VIP from vendors. It's hard to convert those. Is there some cosim approach being looked at? Thanks.

Do you support uvm_component_param_utils? Any alternative approach? Any example?

I will send a dummy test case and see what you might suggest. How well is the sv2py.pl to migrate things over to Python? I am seeing some issues. Thanks...