Satnam Singh
Satnam Singh
Upon reflection, the word `simulate` is perhaps not the best choice and maybe we should revert to `semantics` or some other name that causes less confusion.
I can't load up generated Haskell files or compile them with `ghc --make`. ``` ~/silveroak/examples$ ghci AdderTree.hs GHCi, version 8.10.3: https://www.haskell.org/ghc/ :? for help Loaded GHCi configuration from /usr/local/google/home/satnam/.ghci [1...
https://www.haskell.org/ghc/download_ghc_9_0_1.html
We have a combinational bitonic sorter. A realistic bitonic sorter would be pipelined. One easy way to do this is the make a variant of the two sorter that has...
We use `nat` to describe the size of vectors, and `nat` is what is used in `Vector.t`. However, we never want to generate zero length vectors in our generated SystemVerilog....
I'm working on some debugging and making changes to some SystemVerilog `*.sv` files. However, I can't track what changes I am making because I think we `.gitignore` SystemVerilog files so...
Consider upgrading our CI and the install instructions to use [Coq Platform 2021.02.0](https://github.com/coq/platform/releases/tag/2021.02.0).
My local build was broken, which I fixed up by removing a subdirectory created for FPGA implementation. I see that there is a Verilog file at: ```console $ find ....