rsetaluri
rsetaluri
fault depends on [coreir](https://github.com/rdaly525/coreir) and [pycoreir](https://github.com/leonardt/pycoreir) which contain binary distributions of C++ code. Unfortunately, this code has neither been tested on nor built for Windows. The easiest route would be...
I think the type hierarchy should look like: - Signal * Digital (for backward compat) - Bit - Clock - ... * Real * Elect * ... I think we...
Yeah we want to do this. In the first pass we simply did `print(port, format_str)` but I want to do the following (from #28 ) > Wondering if we can...
We've had some discussions about this and very much want to support this. I think there was some issue regarding verilator support of internal values though...
Good idea, I'm on board for that. So just to be clear, the most-user facing functions (e.g. `Tester.poke/expect`) should have promotion logic (e.g. python `int` to `magma.uint`), and the interface...
Closed by merging `when-detech-latches` -> `when-latest`.
I think there's a few overlapping issues here (you are probably aware of them already, but just writing them out for documentation/discussion sake). 1. Overriding `__call__` for circuits. I actually...
I don't see this as being categorically different from making all the operators more loose w.r.t. bit-widths, e.g. we could also say `+` should be more flexible as a frontend....
Ok, I see. I misinterpreted the intent here. Would also be ok with that as part of the base spec. for shift.
Closing for #1113, since for some reason this can't be rebased...