Richard Meadows

Use the prescaler to set the fastest ADC clock below or equal to this limit Addresses #374 TODO: - [ ] Don't use Boost mode below 20MHz? - [x] Helpful...

Update sdmmc support

3

Update sdio-host version and improve eMMC support

DFSDM

4

Beginning of DFSDM support. Needs work in upstream PAC crate first, register addresses from SVD are incorrect.

No QSPI support for memories

4

Some of the features that would be required to communicate with memories over QSPI (instructions, dummy cycles..) are not supported

Implement tick_timer() for lptimers

4

Ref https://github.com/stm32-rs/stm32h7xx-hal/pull/114 The `tick_timer` method is not implemented for LPTIM[1-5] *Is there some limitation of the LPTIMs that makes it difficult?* The LPTIMs require a specific initialisation sequence (for example,...

ResetEnable trait methods require ownership

4

The [`ResetEnable` trait](https://docs.rs/stm32h7xx-hal/0.6.0/stm32h7xx_hal/rcc/rec/trait.ResetEnable.html) is implemented for Peripheral Reset Enable Control (PREC) [ZSTs](https://doc.rust-lang.org/nomicon/exotic-sizes.html#zero-sized-types-zsts). However, its methods require `self`, so it cannot be used when we only have a `&mut-` reference to...

Tracking Issue for Revision V silicon

5

ST has released a new silicon revision for the `H742/742/750/753` with significant changes. * [eevblog](https://www.eevblog.com/forum/microcontrollers/stm32h7-series-revision-beware-of-the-changes!/) * [ST community](https://community.st.com/s/question/0D50X0000Aixasy/stm32h7-cpu-speed-increase) Please report or tag issues with Revision V here! Also see [upstream](https://github.com/stm32-rs/stm32-rs).

Structure of examples folder

2

Is the structure of the examples folder suitable? Should we add board-specific examples here?