Painting

Failed when entering docker container

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### System information - **OS Platform and Distribution (e.g., Linux Ubuntu 18.04)**: Ubuntu 22 - **Apollo installed from (source or binary)**: gitee - **Apollo version (3.5, 5.0, 5.5, 6.0)**: apollo...

Emu failed

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 Environment: Ubuntu20, latest xiangshan make emu CONFIG=BaseConfig EMU_THREADS=2 -j10 ./build/emu -b 0 -e 0 -i ./ready-to-run/coremark-2-iteration.bin --diff ./ready-to-run/riscv64-nemu-interpreter-so Any solution?

FV on the Current Design

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Hi, I'm trying to add some FVs on the current design, is there any cmodel/golden?

Learning NVDLA CMAC HW Code

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cmac 分为两个大的部分，cmac_reg和cmac_core。 reg部分负责和csb和dp交互，core负责计算。ping-pong reg，在官方文档里有介绍。 重点说说core， 因为core是要计算weight和data的向量积的，其中weight是要被缓存的，然后data不断被push进去。所以weight的部分先被存入shadow区，然后有data进来并满足csc那边进来的stripe的start&end的条件的话，拿出来卷积。 还有几个retiming的模块。。。这个就不说了。

chisel实现的部分nvdla

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众所周知，riscv的硬件描述语言是chisel，但是nvdla的主要部分是由verilog实现的。目前，riscv调用nvdla采用的是chisel内部的blackbox功能。这会造成很多拓展性的麻烦，例如，规划统一的pipeline，部分调用nvdla的计算单元。为此，我正在使用chisel重新写nvdla。希望多提宝贵意见。 这是我的repo: [https://github.com/redpanda3/soDLA](url)。

hi, I got an error message in chipyard which returns the error code of 7, what's that mean? Any booklet?

Any Recomended Python Versions?

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## Environment - Klayout Version: .29.4 - OS/Platform: ubuntu20 python version: 3.8 ## Expected Behavior When klayout has launched, there should be no error in the terminal. ## Actual Behavior...

Any result compared to the real t5?

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Is the pdk accurate enough? Since a7 v t7 has around 50% differences in synthesis by my experimental trial.

Hi, Dinesh, During the verification in caravel_hkspi, there might be an inconsistency between the ctech_clk_buf in aes_top and ctech_clk_buf itself.   One solution is to reduce the power pins...

Iverilog Version

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 Hi Dinesh, I have a problem when verifying the user_usb, the iverilog I'm using gives me a warning like this, could you tell me which iverilog you are using?