Ross Daly
Ross Daly
I think setting up a gitter channel would be a good idea.
Yeah, I think there are some ambiguous semantics. Specifically step() without duration is ambiguous in terms of multiple clocks. I think there are a couple ways to resolve this. lets...
For stubbing, would it also be desirable to instance "term" instances for the inputs? If you want this behavior in CoreIR, blackboxing can be done by just removing the module...
@rsetaluri, @dillonhuff: I have a hunch this is due to implementing the simulation step function as ``` def step(): eval() flip_clock() ``` vs: ``` def step(): flip_clock() eval() ``` The...
If the user specifies verilog instead of systemverilog, the 'flattentypes" pass could be run so that we do not run into the ND-array issues.
I agree with defining these as additional methods instead of changing the default semantics of add/mul. I would also advocating defining these circuits in mantle.
I suspect the issue is that I check to make sure the top module has a definition. But CoreIR does not (currently) recognize that the verilog metadata is a definition.
A hacky way to fix this is to add an empty coreir definition to the module.
Resynced this with the current dev branch. This pass should be useful for @makaimann
Another: https://github.com/jinwookjungs/datc_robust_design_flow