pyuvm

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Add RAL Analysis Document

1

This submission adds a new document, `docs/ral_analysis.md`, which contains an analysis of the current state of the `pyuvm` register layer implementation. This analysis compares the existing code to the IEEE...

google-labs-jules[bot]

Move TinyALU clock generation to cocotb testbench

1

This refactoring moves the clock generation for the TinyALU example from the VHDL design to the `cocotb` testbench. Specifically, the changes are: - The internal clock generation process in `tinyalu.vhd`...

google-labs-jules[bot]