Move TinyALU clock generation to cocotb testbench

[google-labs-jules[bot]]

This refactoring moves the clock generation for the TinyALU example from the VHDL design to the cocotb testbench.

Specifically, the changes are:

• The internal clock generation process in tinyalu.vhd has been removed.
• The clk signal in tinyalu.vhd is now an input port.
• The TinyAluBfm in tinyalu_utils.py now creates and starts a 2us clock on the DUT's clk pin.

This centralizes clock management within the test environment, making the setup more flexible and aligning with standard verification practices.

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PR created automatically by Jules for task 8967099609063795420

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