Rafael do Nascimento Pereira

no color diagnostics (coc.nvim + ccls)

2

## Problem When using neovim-qt, the diagnostic information (coc.nvim + ccls (lsp for c/cc++) shows no colors, in contrast to using neovim directly, as shown in the images below: Running...

It is not clear what this plugin does

5

My apologies in advance, if either my question is stupid or if I am blunt, but it is not clear what the plugin additionally does, when compared to fzf.vim. What...

Add command line option for choosing builder

1

Add command line option, to enable the user to choose which builder he/she wants to use. Suggestion: `--builder BUILDER specify the builded to be used` By adding it, it would...

It would be helpful to be able to use environment variables in the `vhdl_ls.toml` file, so: 1. paths are not hardcoded 2. easier to share the same `vhdl_ls.toml` file across...

question: support to extended identifiers in the VUnit VHDL Parser?

2

Hello, When using PeakRDL-regblock-vhdl in tandem with VUnit I have the following error executing the run.py script: (although it does not interrupts the testbench execution) ```sh ython3 run.py Traceback (most...

The VC [AXI4 Lite manager](https://github.com/VUnit/vunit/blob/master/vunit/vhdl/verification_components/test/tb_axi_lite_master.vhd) lacks the reset port, making it difficult to perform a verification on scenarios where the DUT needs a reset to initialise its internal logic. In...

Question: execute command before generating a project using Vivado

3

I am using PeakHDL to store synthesis time and date in an AXI4-Subordinate IP Core and have to execute register generation every time the project. containing this IP Core, is...