Raghuveer Devulapalli

BLD: Add compile and runtime checks for AVX512FP16 and AVX512_SPR

3

Adding compile and runtime support for upcoming Intel Xeon Sapphire Rapids.

ENH: Vectorize FP16 umath functions using AVX512

6

This patch leverages the` vcvtps2ph`, `vcvtpd2ps `instructions and float32 SVML functions to accelerate float16 umath functions. Max ULP error < 1 for all the math functions.

ENH: Vectorize quicksort for 16-bit and 64-bit dtype using AVX512

2

This patch adds AVX512 based 64-bit on AVX512-SKX and 16-bit sorting on AVX512-ICL. All the AVX512 sorting code has been reformatted as a separate header files and put in a...

ENH: Convert fp32 sin/cos from C universal intrinsics to C++ using Highway

6

This patch is to experiment with highway and see how we can leverage its intrinsics using static dispatch. I would think these are the minimum requirements: - [ ] passes...

Split different configurations of meson

The error is a problem when building NumPy with baseline cpu feature of avx512f.

32-bit argsort uses ymm registers: we can switch to zmm registers (use 2x i64gather instructions) and add new bitonic networks.

I suspect this function https://github.com/intel/x86-simd-sort/blob/7d7591cf5927e83e4a1e7c4b6f2c4dc91a97889f/src/avx512-16bit-qsort.hpp#L65 can be improved with fewer operations. See: https://github.com/numpy/numpy/blob/0bd56e7ec12f8ceeb8d082340e71e60b873d5c57/numpy/core/src/npysort/npysort_common.h#L153 for reference.