Quswar Abid

I think there is no support for RISCV-DV for ZiCond ext. yet. @asimahsan1990 maybe you need to get that added first AFAIK since Ibex uses that in its verification environment.

Hey @mp-17 I think this might be a good opportunity to explore few options regarding test suites/generator already available. I have made a riscof plugin for ARA and got it...

Yes, sure. I'll drop you a mail soon to schedule a meetup. Looking forward to it! Meanwhile you have a great weekend @mp-17 😊

Encountering the similar problem on latest ARA:main Got advised to change the optimization flag and it fixes the problem but now the simulation is taking forever to finish (Related Issue...

I found this [update](https://github.com/pulp-platform/ara/commit/5327d45a27fbca65ba76d6bf83bc20803787390a) of no good use. I bumped the verilator version back to v4.214 and it worked out for me.

@llhe110 I bumped the verilator version back to v4.214 and it worked out for me. To do that, edit VERIL_VERSION in `ara/Makefile`. Then run `make verilator` in `ara/` to build...

Well dumping in vcd IS supported by Verilator, and ideally replacing `--trace-fst` with `--trace` in [this line](https://github.com/pulp-platform/ara/blob/5b66cc0996acfb27aa5eff4410d67707255b2e8e/hardware/Makefile#L224) should work. But I get this issue when I try this: ``` quswarabid@quswarabid:~/ara/hardware(main)$...

> @llhe110 @quswarabid > > Did it work for you ? > If not what are the changes you did or any insights would be useful > Hi @Tanishqgithub, I...

Can't recreate this and debug this issue @Tanishqgithub I don't have this repo setup right now

Is there a way to re-create the issue?