fpu
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37-11 * 3 calculation error, Who can fix it。 @svenstucki , @alessandrocapotondi @gtagliavini @andreaskurth @Yaooooo
hello: I have some questions about how LZA module works? As leading zero anticipator, it serves to predict the leading zero counts of result while adding, so that normalization can...
Hello, FPU module computes wrong results for the ADD operation of (-0) and (-0). The returned result is (+0) instead of (-0) according to the IEEE standard BR, Nicolae
In the file `fpu_shared.sv` a parameter called `C_FLAG` is referred, which I can't find in the imported package `fpu_defs`. ```verilog logic [C_FLAG-1:0] Flags_S; ``` I'm assuming it is a typo...