projf-explore
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projf
Project F brings FPGAs to life with exciting open-source designs you can build on.
The `lib/clock/xd.sv` module has ports named `_i` and `_o`. The port names suggest signals are inputs and outputs even when they're not. Source and destination based naming would be clearer....
On page https://projectf.io/posts/numbers-in-verilog/ you mention: > Say you’ve got a bit-endian ... You probably mean big > ... byte from I2C and want to convert it to little-endian. Alas, you...
We don't check the SDL/Verilator screenbuffer array index is valid. ```c++ Pixel screenbuffer[H_RES*V_RES]; // update pixel if not in blanking interval if (top->sdl_de) { Pixel* p = &screenbuffer[top->sdl_sy*H_RES + top->sdl_sx];...
This adds support for the * graphics/framebuffers * graphics/pong examples for the ULX3S board. Has been tested on my board.
We use `bitmap_addr` to calculate the memory address from drawing coordinates. Address calculation requires three cycles, so we delay write enable (`we`) to match. We need to delay the colour...
Have you considered opening a discussion forum here on github? A place where people can float ideas that aren't necessarily "issues"? Just an idea, thanks for your good work either...
Sup-pixel precision gives smoother movement. We could support Q12.4 precision when drawling while retaining 16-bit coordinates. Signed Q12.4 provides for a range of -2048 to + 2047, which covers any...
When two triangles share an edge, we need to decide which triangle draws that edge. The standard approach is to draw the top and left edges. Implementing the top-left rule...
If we draw a triangle outline and a filled triangle with identical vertices, they don't always match. This seems to be a problem on some edges where there are multiple...
The current Verilog maths and Python fixed-point test modules choose different values in some cases where the inputs can't be precisely represented in binary. We should output the model a...