Project F - FPGA Development

Project F is a little oasis where you can quench your thirst for FPGA knowledge, where you can find accessible, open-source designs to learn from and build on. Our main projects are the Verilog Library and FPGA Graphics tutorial series; read on to learn more.

Get an introduction with About Project F, follow @WillFlux for updates, and join the FPGA discussion on 1BitSquared Discord. Take a peek into the future with our roadmap.

Image generated by the greetings demo from Ad Astra on a Nexys Video FPGA board.

Verilog Library

The Project F Library includes handy Verilog designs for everyone. From framebuffers and video output to division and square root, rom and ram, and even circle drawing. You can freely build on these MIT licensed designs.

See Library for details or discover about the background to the Library.

FPGA Graphics

In this series, we learn about graphics at the hardware level and get a feel for the power of FPGAs. We'll learn how screens work, play Pong, create starfields and sprites, paint Michelangelo's David, draw lines and triangles, and animate characters and shapes. Along the way, you'll experience a range of designs and techniques, from memory and finite state machines to crossing clock domains and translating C algorithms into Verilog.

If you're new to the series, start by reading Beginning FPGA Graphics.

• Beginning FPGA Graphics: Designs - Blog
• Racing the Beam: Designs - Blog
• FPGA Pong: Designs - Blog
• Display Signals: Blog (no demos with this post)
• Hardware Sprites: Designs - Blog
• Framebuffers: Designs - Blog
• Lines and Triangles: Designs - Blog
• 2D Shapes: Designs - Blog
• Animated Shapes: Designs - Blog

Hello

A three-part introduction to FPGA development with Verilog; currently available for two boards: the Arty A7 and Nexys Video.

• Hello Arty: Designs - Blog 1 - Blog 2 - Blog 3
• Hello Nexys: Designs - Blog 1 - Blog 2

Maths and Algorithms

Maths & Algorithms is our lastest tutorial series:

• Numbers in Verilog - working with signed and unsigned integers
• Multiplication with FPGA DSPs - efficient multiplication with DSPs

There are maths demos in this repo to accompany the series.

Stay tuned for more parts later in 2022.

Demos

Assorted demo projects:

• Ad Astra: Designs - Blog - greetings with starfields and hardware sprites
• Life on Screen: Designs - Blog - Conway's Game of Life in logic

Requirements

FPGA Architecture

Our designs seek to be vendor-neutral, but some functionality requires support for vendor primitives. We currently support two FPGA architectures:

• XC7 - Xilinx 7 Series FPGAs, such as Spartan-7 and Artix-7
  • BUFG, MMCME2_BASE
  • HDMI support: OBUFDS, OSERDES2
• iCE40 - Lattice iCE40 FPGAs, such as iCE40 UltraPlus
  • SB_IO, SB_PLL40_PAD, SB_SPRAM256KA

We also infer block ram (BRAM), see lib/memory.

Porting to other architectures should be straightforward.

SystemVerilog?

We use a few simple features of SystemVerilog to make Verilog more pleasant:

• logic type is safer and less work than using wire and reg
• always_comb and always_ff to make intent clear and catch mistakes
• $clog2 to calculate vector widths (e.g. for addresses)
• enum to make finite state machines simpler to work with
• Matching names in module instances: .clk_pix instead of .clk_pix(clk_pix)

I believe these features are helpful, especially for beginners. All the SystemVerilog features used are compatible with recent versions of Verilator, Yosys, and Xilinx Vivado. However, if you need to use an older Verilog standard, you can adapt these designs without too much trouble.