Pekka Jääskeläinen
Pekka Jääskeläinen
https://github.com/parmance/OpenCL-Docs/blob/abort/extensions/cl_ext_device_side_abort.asciidoc
Implements the relaxed printf AS extension for flat address space targets (read: CPUs). Supporting disjoint AS targets would require a bit more work. The extension is [here](https://github.com/parmance/OpenCL-Docs/blob/eprintf/extensions/cl_ext_relaxed_printf_string_address_space.asciidoc).
With pocl: ``` $ POCL_DEBUG=1 bin/mnist -platform=0 -device=0 -opencl Loading the mnist database. ... [2019-04-01 15:23:40.903036977]POCL: in fn POclCreateKernel at line 80: | ERROR | CL_INVALID_KERNEL_NAME Can't find a the...
In the RISC-V tutorial we now need to add a dummy Verilog file although we do not want to generate Verilog, which seems unoptimal.
The RISC-V tutorial asks to install a custom op module there, but it's not found.
It should at least search from the build (source) tree in case TCE_DEVEL_MODE=1 to enable running/testing the build tree without relying on an installed OpenASIP.
Add a link from the tce repo.
Change to OpenASIP.