peterhchen

How to set the LLVM_HOME?

3

export LLVM_HOME=/path/to/your/llvm/installation 1. What is "/llvm/installation" example? 2. Do we have to build "llvm/installation"? 3. Can you give us the link of step-by-step how to build "llvm/installtion"? Thanks, Peter H....

Disable performance, power, or area

5

Is there a way to control 1. Performance only 2. Power and area only

How to fix error; build/X86/gem5.opt configs/example/se.py -c tests/test-progs/hello/bin/x86/linux/hello

49

in /workspace/gem5-addlin, > build/X86/gem5.opt configs/example/se.py -c tests/test-progs/hello/bin/x86/linux/hello Error: AttributeError: Values instance has no attribute 'accel_cfg_file' How to fix this error? [071_CompileRun_Gem5_Aladdin_C_code_CommonZone.pptx](https://github.com/harvard-acc/gem5-aladdin/files/7500284/071_CompileRun_Gem5_Aladdin_C_code_CommonZone.pptx)

Exercise: Sign-magnitude Numbers Suppose you wanted to use a sign-magnitude representation and want to reuse all of your DSP generators. Typeclasses enable this kind of ad-hoc polymorphism. The following example...

Try uncommenting the print statment == "statment" should be "statement"

twice the number of taps "worth" of data should be twice the number of taps "width" of data?

Updating the register: "concatentation operator" should be "concatenation operator"

typo: "preceeding" should be "preceding"

2

launches a concurrent code block, additional forks can be run concurrently to this one via the .fork appended to end of the code block of the preceeding fork == "preceeding"...

The Verilog looks almost the same as before, though the register name is generated instead of explicity defined. === The Verilog looks almost the same as before, though the register...