sv2chisel
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(System)Verilog to Chisel translator
**Describe the bug** recognize constan that is not in length of value as error **To Reproduce** verilog:  report:  verilog without constants:  report:  if not use `reg_num,...
**Describe the bug** token clean on function return type is probably missing **To Reproduce** function with inner comments **Expected behavior** proper emission of comments
**Describe the bug** Some asTypeOf could be avoided **To Reproduce** - function returns are cast even with the right type - subfields might be cast uselessly **Expected behavior** The right...
**Describe the bug** sv2chisel is too conservative on parenthesis **To Reproduce** `a && b && c` is translated into `(a && b) && c` **Expected behavior** `a && b &&...