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(System)Verilog to Chisel translator

Results 4 sv2chisel issues
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**Describe the bug** recognize constan that is not in length of value as error **To Reproduce** verilog: ![image](https://user-images.githubusercontent.com/60850531/154936838-3bbd7cde-8329-41fb-8501-d74715f1eee0.png) report: ![image](https://user-images.githubusercontent.com/60850531/154937008-2fc77155-fb93-461f-b3d4-903032fdf4b9.png) verilog without constants: ![image](https://user-images.githubusercontent.com/60850531/154937188-34d653ba-b91e-45d5-aca8-7d9164f573c9.png) report: ![image](https://user-images.githubusercontent.com/60850531/154937258-d979b812-b14e-47f4-aeba-916871b57683.png) if not use `reg_num,...

bug

**Describe the bug** token clean on function return type is probably missing **To Reproduce** function with inner comments **Expected behavior** proper emission of comments

bug

**Describe the bug** Some asTypeOf could be avoided **To Reproduce** - function returns are cast even with the right type - subfields might be cast uselessly **Expected behavior** The right...

bug

**Describe the bug** sv2chisel is too conservative on parenthesis **To Reproduce** `a && b && c` is translated into `(a && b) && c` **Expected behavior** `a && b &&...

bug