olafvandenberg

I'm not sure I fully understand the issue. The pop_axi_stream with reference can be fully queued up, without any cycles in between. When using the pop with a direct await...

Ok I get it.. It is an unwanted side effect of the change needed for the clock re-alignment. I'll have a look today to see if I can think of...

So I had a closer look, and I can't seem to reproduce this behavior. There is a small glitch on ready if you do back-to-back transfers while using the blocking...

I'm using Modelsim PE 10.7b. For the test I did a small modification in the tb_axi_stream.vhd. the test I modified is "test back-to-back passing check", I've simply copied the test...

I pulled the branch axis/synthetic from eine's fork, and ran the array_vcs example tb_axis_loop. I had to comment out some psl stuff in the fifo that breaks compilation on my...

The delta cycle is proven in my opinion. I've added one by inserting a wait for 0 ps; right before the tready

I would like to find a proper fix for this issue. In my opinion the difficulty is that in the current setup you can't predict whether there will or will...

@eschmidscs I think that would give consistent 50% behavior, so always >= 1 low cycle. (as mentioned in one of my earlier posts) The checking for pop transactions is actually...

@eschmidscs I believe so, as the forced delta would be inside the while loop on 'not is_empty(message_queue)'. I think the problem is that the blocking pop is made of a...

@eschmidscs yeah, I checked and I'm able to fix the issue by adding two consecutive 'wait for 0 ps;' statements right after the reply() call. I believe a separate notify...