Nick Knight

How about if we require the trailing alphabetical character must not be "p"? EDIT: oops, I see @jrtc27 already pointed this out https://github.com/riscv/riscv-v-spec/issues/729#issuecomment-912407993

My understanding is that this is the goal of https://github.com/riscv/riscv-asm-manual , although it appears there's a lot of work to be done on that project. Your contributions would be appreciated!

@Omarezz123 1. Go here: https://github.com/riscv/riscv-isa-manual/releases (I have this in my browser's bookmark toolbar). 2. Identify the latest release: it should be near the top of the page. 3. Click "Assets"...

RISC-V vector crypto enhancements to OpenSSL have been proposed: https://github.com/openssl/openssl/pull/20149 This PR remains labeled as draft while the ISA spec is still being developed by the Cryptographic Extensions Task Group:...

The vector crypto proposal does not add architectural state beyond what is already in V. It's purely instructions. The (ratified) scalar crypto extensions include Zkr ("entropy CSR"), which does add...

My understanding is: "Yes; No", based on the following text: > For floating-point operations, the scalar can be taken from a scalar f register. If FLEN > SEW, the value...

> This can allow people to easily move the lower bits of, let's say, F64 number, to vector register so that they can do bit-level operations on mantissa without worrying...

> Control and State Register (CSR). I think we prefer "status", not "state". I also don't think it's necessary to redefine the acronym in each chapter. I don't have strong...

My personal opinion is (and always has been) that the following text: > RISC-V defines a separate address space of 4096 Control and Status registers associated with each hart. hidden...

My understanding is that a "hart" is a fundamental notion in this abstract computation model, and the authors are mentioning hardware threads only by analogy, to illustrate how this abstract...