narutozxp

The problem now is that I first generate the RTL file of the FPGA through openfpga, and the layout and routing results of the corresponding benchmark. But we found that...

I know that openfpga provides a file to describe the pin constraints, but I don't know how openfpga calls this file. Or should I use vpr --place_file place_file_name.place for my...

Thanks a lot, but I can't use pcf2place with openfpga in version 1.1.0 (latest release). Does this feature currently only exist in the beta version?

@gmartina Hello, there is the example code. According to the image(OUTlINE), Teros seems to identify the signal name as the signal type. ```verilog module misc_ctrl ( /**********************/ /* input */...

@gmartina Besides, your demo seems to show the function of vscode itself, not TerosHDL.

@vaughnbetz thank you for your kind answer. However, this will result in a heavier load for input wires, but will not improve routing. For example, if we have the following...

I encountered a very strange problem, that is, if I disable `highlight` in the treesitter configuration, and then run `vim.treesitter.start()` in the open buffer, the colored brackets can be updated...

When using $NVIM_APPNAME, my configuration will not be able to download lazy.nvim, so it is not easy to implement the above test. Maybe the behavior is due to this code...

Thank you for your guidance, the behavior shown by minimal configuration is indeed correct

In my original environment, the best solution is to refer to the above solution, add an automatic command, and disable highlight in treesitter. ```lua require 'nvim-treesitter.configs'.setup { -- ensure_installed =...