Rick Altherr

Playing around a bit more, I think I was wrong about the tolerance being spread across the measurement time. The PLL only gets updated at the end of the next...

Updated the PR with the numerical accuracy fix for the integral and to adjust the PLL to 1440kHz loop frequency and loop dampening of 0.25.

Neat! I haven't had a chance this week to poke at it. I do think I have a mistake in the phase error calculation. It should _not_ be divided by...

The delta between the ideal bitcell center and the actual edge is the total phase error at that instant according to the PLL clock. I originally added the divide by...

phase_step is nco-ticks/timer-tick write_bc_ticks is timer-ticks/mfm-tick So phase_step*write_bc_ticks is nco-ticks/mfm-tick and current_bc_left_edge is supposed to be in nco-ticks (modulo 32-bits). phase_error should also be in nco-ticks. On Fri, Jan 26,...

Finally found some time to revisit this. I cleaned up https://github.com/mx-shift/Centurion_Floppy/tree/main/flashfloppy_to_hfe quite a bit and replaced all the nco_* variations with a parameterized version as you had done in your...

Nope. That seems to be pretty difficult to do. On Tue, Feb 20, 2024, 12:17 AM Keir Fraser ***@***.***> wrote: > Nice. Can it tolerate 400ns precomp in a 1.44m...