Michael Schaffner comments

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                                            Michael Schaffner

Support Synopsys Design Compiler (DC) for Synthesis

@olofk, if you need someone to help with this (including running some tests) I can assist.

Support Synopsys Design Compiler (DC) for Synthesis

Ok so DC is a bit tricky, since in addition to the tool flow itself, you need to set up technology specific libraries to make this work. Hence, it is...

Support Synopsys Design Compiler (DC) for Synthesis

Let me know if you need more info or whether I should test something. I still need to think about how we can check for success at the end of...

Support for JasperGold for Formal Property Verification

Ok so I think we could build this backend by reusing the AscentLint flow that is already in place. It would be great if we could invoke the tool in...

[lsp] Spawning language server with cmd: `verible-verilog-ls` failed with error message: EIO: i/o error

@hzeller

[lsp] Spawning language server with cmd: `verible-verilog-ls` failed with error message: EIO: i/o error

Was there anything specific that you had to do to get it running?

[lsp] Spawning language server with cmd: `verible-verilog-ls` failed with error message: EIO: i/o error

FYI: I am running this on gLinux with Sublime build 4126 and it works fine for me.

Add Google's Verible verilog formatter for verilog, systemverilog files

Interesting, thanks for the pointer @fangism ! @eunchan for visibility

FPU Configuration Discussion

I would also go for structs. This seems to work fine with VCS, Verilator, Questa, DC and Vivado so far. Have a look at [this](https://github.com/pulp-platform/ariane/blob/598b8e447a1d9421ab4a52b6a910b33acca0d6c8/include/ariane_pkg.sv#L36-L78) for an example

FPU Configuration Discussion

Ok I see. The array-of-structs sounds like a good idea to try out then...