Mehdi Saligane

Hi @stdavids I was confused as well: usually VNW is the pin connected to Nwell but here it is called VPB. Similarly, VPW is the pin for Pwell, and here...

@robtaylor see attached [sky130_fd_sc_hd__tt_025C_1v80.zip](https://github.com/google/skywater-pdk/files/6251392/sky130_fd_sc_hd__tt_025C_1v80.zip)

This seems to work however, there is an issue with a few cells: `'sky130_fd_sc_hd__dlclkp_1'`, `dlclkp` and `sdlclkp `cells ` Error: Line 57389, Cell 'sky130_fd_sc_hd__dlclkp_1', pin 'M0', An invalid attribute 'related_ground_pin'...

@RTimothyEdwards It doesn't sound like the upstream repos are being updated. https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hd/tree/master/tech Am I missing something?

Thanks @RTimothyEdwards and @agorararmard . BTW, is the MINENCLOSEDAREA needed in the other libs such as `sky130_fd_sc_hs`. If so, then we need to update the other `tlef` files. Thoughts?

Hi All I agree that it should be declared as an input. This is what I think would be the right LEF description of the hd diode cell as an...

@RTimothyEdwards That should work too!

@mithro I didn't need to read verilog in my flow but I will need to read it or cdl at some point. I can try to look at this closely...

It is needed during the LVS checks (or digital functional simulation ). I usually use cdl files for both of these. I can read these files and see what issues...

I agree as well. Based on this description:  As long as all the sub-cells in the same cell folder(same cell with different drives) have the same "cell_footprint" attribute,...