Mohamed Hosni
Mohamed Hosni
Well, we never inferred tri-state buffers in the RTLs using ``` assign out = en ? in : 1'bz; ``` we usually specify the std cells in the RTL to...
Hi, In the second example, most of the buffers are either for long wires or max cap. Typically, the fanout buffers are names start with `fanout`. Also, in the first...
I ran `make ship` and `make truck` and there are no issues with either. I also ran `make caravel_core` and `make caravan_core` in openlane and there is no issue.
@M0stafaRady, @dlmiles : I just looked at the waveforms again, For example writing data as in this for loop here: https://github.com/efabless/caravel_aes_example/blob/a1331908121e225b8cd6064d06b0bb2f7e87401a/verilog/dv/cocotb/encipher_test/encipher_test.c#L27 The CPU takes 8120 clock cycle between each write...
Clear was updated based on new updates in SOFA. The HDL updates can be found here: https://github.com/lnis-uofu/SOFA/tree/master/SOFA_A/FPGA88_SOFA_A Can you elaborate more on the issues you're seeing?