Maciej Kurc
Maciej Kurc
#### Description Currently for models with no pin-to-pin relations defined VPR assumes that their outputs become constant generators even though such models have inputs and they are connected to active...
This PR contains some general fixes #### Description The PR fixes build errors when `VERBOSE` is defined. It also fixes VPR ignoring netlist verbosity commandline option. #### Related Issue ####...
This PR adds support for multipliers and RAMs (as individual cells) from ASSPL and ASSPR in PP3e.
~Attempt to solve https://github.com/SymbiFlow/symbiflow-arch-defs/issues/1991. Expecting CI to fail for now due to `BUFHCE` handling in fasm2bels.~ This PR fixes the incorrect `PLLE2_BASE` techmap (https://github.com/SymbiFlow/symbiflow-arch-defs/issues/1991) plus updates the `prjxray-db` so that...
This PR modifies the tile splitter to allow explicit specification of which sites go to which tiles. Moreover, split tile position offsets can be arbitrary as well. **The code is...
This PR contains: - the `litex/mini_ddr` design ported to Nexys Video, - the `litex/base` design ported to Nexys Video (disabled for now), - a new LiteX without ethernet `litex/base_no_eth` for...
This PR adds the following capabilities to the utility script: - Debugging output. It has to be enabled in the code via the `DEBUG` global variable - Handling of incomplete...
With https://github.com/SymbiFlow/symbiflow-arch-defs/pull/1729 merged the `MMCME2_ADV` primitive is supported. However the `MMCME2_BASE` which is a subset of it is not supported yet. What needs to be done to add the support...
There are fuzzers `100-dsp-mskpat` and `101-dsp-pips` that target Xilinx 7-series DSP tiles. They should already provide solution for all routing and most of DSP configuration bits. There is an open...
In its current state (6e3f053) the prjxray database contains documentation for bits controlling the following `MMCM` features: - Internal register bank controlling: - Multiplier - Dividers (both integer and fractional)...