Michael Rogenmoser

AXI4 on chip memory slave

2

This PR adds the `axi_to_mem` module to translate AXI4 to a simple memory protocol. This PR partially replaces #115 and #213.

This PR adds a banked variant of `axi_to_mem` for higher throughput. This PR also adds a test for `axi_to_mem_banked`, which also tests `axi_to_mem` as it is called within the new...

AXI4 on chip memory slave

1

Rebase of the relevant changes in #115 on the current master This adds two modules: - `axi_to_mem`: Slave module, max throughout simultaneous read/writes 50%, read or write 100%. - `axi_to_mem_banked`:...

AXI Demux could be extended to send requests with same ID to different slaves

6

With multiple outstanding write requests going to different slaves in `axi_demux`, the demux waits for the B responses from the first request before sending the second request (AW) to a...

Add `axi_dumper` and `axi_dumper_interpret` script.

2

This module dumps a log from an AXI bus, which can be analyzed with the interpret script for debugging purposes.

Enforce more consistent type naming

2

Unify type naming across modules, using `axi_req_t` for AXI request and `axi_lite_req_t` for axi lite request. May fix some issues for vivado (see HERO). Similar for `resp` types.

This PR addresses an inconsistent DMA ID in case the `merge` flag is used. The previous implementation would reset the `copy.id` to -1 in case the `copy.merge` flag is set,...

Improves compatibility for fusesoc and vivado xsim and includes a limited test for this in the internal CI. Replaces #232. Fixes #226, #247.

From #98

Rebase of a 2-year old branch: axi_lite_dw_downsizer: Add AXI4-Lite data width downsize conversion module axi_test:rand_axi_lite_slave: R response field is now random axi_lite_sw_converter: Add to synth bench