Michael Platzer

Hi @moimfeld, thanks for reporting this. Indeed, these instructions are currently executed in the same fashion as the regular `vand`, `vor`, etc., with the EMUL always set to 1. Therefore,...

Yes, indeed, these flags are not implemented yet. The [V extension specification](https://github.com/riscv/riscv-v-spec) requires that "Attempts to execute any vector instruction, or to access the vector CSRs, raise an illegal-instruction exception...

Hi @moimfeld, Thanks for this bug report. You are right, the issue is related to the suppressed memory requests. Thanks also for pointing out the issue with the `last` signal!...

Hi @kuoyaoming93 my apologies for the incomplete documentation, I am hoping to improve it very soon! The best starting point for simulating Vicuna with Verilator is to compile your program...

Hi @kuoyaoming93 thanks for the feedback! These CSR registers are part of the main core. I do not know whether these are enabled by default, but the documentation of [Ibex](https://ibex-core.readthedocs.io/en/latest/03_reference/cs_registers.html)...

A slight inconvenience of the changes in #43 is that the Verilator 4.210 is now required to simulate Vicuna. If your distribution only features older versions, you can compile version...

Thanks for pointing this out. The way the cache is currently implemented requires that the line width is larger than the memory data width (i.e., `LINE_BYTE_W` > `MEM_BYTE_W`). I will...

Multiple write ports should never write to the same register in the same cycle. The dispatcher (implemented in `vproc_dispatcher.sv`) maintains a record of outstanding vreg writes and stalls instructions that...

Hi, the code in that file should work properly, but there is no test or reference data. The kernel tests have been used as benchmarks, but are not suitable to...

Hi @Nikhil-311293, this error indicates that the width of the VLSU's operands does not match the width of Vicuna's memory interface. In your configuration file the width of the VLSU...