Michael Etzkorn 明凯

> Try setting it to true, then see if the familiar codelenses appear. Why the change to disable this by default? it's very useful to have the codelenses

Related issue: - https://github.com/chipsalliance/rocket-chip/issues/2920 Some relation to the style guide discussion we had today in the working group since I moved some parentheses to a new line if the config...

To more accurately describe the expected behavior: because there's no mask signal on the AHB end, we're expecting in translating to AHB from TL to only transfer the data on...

@sequencer this is maybe something we can discuss April 6th, but I believe for (4), it'd be reasonable to consider (and I'd be willing to help develop) UVM-based or generic...

Yes, it seems this is an issue with running a test requiring a large stack. By default, the TinyConfig only has a 16KB scratchpad of memory. See: https://github.com/chipsalliance/rocket-chip/issues/430

Unclear if this is outdated, but I'll aim to reproduce this sometime in the near future

It appears hardfloat's mill build is pointing to `3.5-SNAPSHOT` (which probably isn't a good idea). We'll have to have those point to stable versions so that mill doesn't cause this...

I imagine this can be fixed by following the `README`'s instruction for tool-setup https://github.com/chipsalliance/rocket-chip#setting-up-the-riscv-environment-variable

Did you add `CanHaveMasterAHBMMIOPort` to your system's traits? Is `ExtBusAHB` replacing `ExtBus` or are you writing `ExtBus => ExtBusAHB` in your `WithDefaultMMIOPort` config?

Welcome to Scala 2 inheritance antics. I highly encourage posting these sorts of questions on Stack Overflow using the rocket-chip tag since search engines can better index answers and time-to-time...