merry
merry
Framework of ARM64 backend. Aim is for a working A32 support to be done first. This also involves a redesign of how backends are done, to potentially support multiple threads...
Proof of concept that only handles values between `0x0080'0000` and `0x7e80'0000`.
Will need to verify this behaviour. The relevant CPSR execution state bits affected are: * IT * J * T * E The v7 manual specifies that CPSR should be...
- [ ] Track zexts, Track setbits. - [ ] Improve xmm → gpr transfers. [(This code looks suboptimal.)](https://github.com/merryhime/dynarmic/blob/da5d06c32ac0b9cb257dda22e5a1ac9a55ee92c2/src/dynarmic/backend/x64/reg_alloc.cpp#L348)
Fallbacks currently save/restore all register state. This can be reduced to only required registers.
SWP and SWPB are not atomic in multithreaded scenarios.
Required for invalidation during multicore emulation. Also consider not exposing this at all to the user when AddressSpace refactor hits.
Approximate cycle counting more accurately by allowing a cycle model to the specified, which is queried at JIT-time so more slightly more accurate cycle timings can be had. Note that...
Currently we analyse guest code at a basic block level. While this was initially intended to be temporary, evidently there's nothing more permanent than a temporary solution. We would likely...
This is a specialization of the optimization in #87.