Martin Cejp
Martin Cejp
Repro ``` pip install --user -U fusesoc git clone https://github.com/alexforencich/verilog-uart.git fusesoc --cores-root . core list ``` Result: hang!
This unifies the change handling between _slider_ and _number_ widgets and makes it possible to have a property value automatically reflect the widget.
`LGraphNode` has a property `clip_area`, which if set to true, clips all draw operations to the "body" of the node. However, it also causes the node title to disappear: `clip_area...
- added generic fallback (`sans-serif`) to every font specification - enclosed all explicit font names in quotes for consistency and visual difference - `h1` and `h2` elements don't seem to...
Using cocotb v1.7.0.dev0 along with Icarus Verilog provided by [oss-cad-suite nightly](https://github.com/YosysHQ/oss-cad-suite-build/releases) from a few days ago Design: ```verilog module my_design(input logic clk); timeunit 1s; timeprecision 1ns; //logic my_array[0:2097152]; logic my_array[0:1048576];...
Hi, with the option `process=True` vertices get merged despite different colors. Trimesh 3.10.0 ```python import trimesh vertices = [ (0, 0, 0), (0, 0, 1), (0, 1, 0), (0, 0,...
Hello! I am trying to use this image to run a CI job via GitHub Actions. My workflow is set up like this: ```yaml compile-rtl-quartus19: runs-on: ubuntu-latest container: chriz2600/quartus-lite:19.1.0-2 steps:...
First of all, thank you so much for your work on this project. It really is a game changer for C++ docs. Now, I'm struggling a bit to explain this...