Max Strange

Values of 33-64 don't work with verilator

2

https://github.com/leonardt/fault/blob/f8373e14dfa96d1cab6676387e17202c10df16c4/fault/verilator_target.py#L21-L22 Also needs `import platform` again

segfault when using prototype components.

44

I am experiencing an issue where any attempts to generate a Verilog for my test bench is segfaulting. ``` %> coreir --version v0.1.51 ``` This error can be reproduced by...

Vectorization + Sequence Emit

1

Joey, I was hoping you could help me out with your autovectorization and make it generate single width addresses for items internally represented as multiple ports. For instance, the agg...

As per current cuSPARSE documentation - cusparseCreateCsr's 5th argument needs to != NULL when rows > 0