Matthew Ballance

Standalone reference to 'this' is marked as a symbol-resolution error

9

Thanks for taking the time to report this. Can you attach an example that shows the issue? (Must be openly licensed, ideally in test_regress format.) I've modified t_class_uses_this.v to show...

I'm following the integration flow in caravel_user_project, with the caravel subproject pointing to caravel-lite. I receive an error about the pin_order.tcl file if fixed_wrapper_cfgs.tcl does not set script_dir internally. This...

Support updating the definition of rangelists

2

@mballance, I have created randobj's that store rangelist values in their properties. These properties are then used in constraints. My problem is that updating the value of a rangelist-holding property...

Covergroup instances are currently named , _1, etc. A mechanism should be provided that would allow a user to specify a more-meaningful instance name

### Discussed in https://github.com/fvutils/pyvsc/discussions/185 Originally posted by **jiyong00** August 8, 2023 Does anyone know how to write "default" as vsc.coverpoint in systemverilog style coverpoint as follows? ``` zero_delay : coverpoint...

OpenRAM branch to use

2

Hello, I'm trying to re-run the generation steps here as a way to learn more about OpenRAM with sky130. I'm using the main branch of [OpenRAM](https://github.com/VLSIDA/OpenRAM), but this appears to...

Bootstrap instructions are debian specific

9

@mithro says "Everything else should work but the bootstrap is debian specific."

This PR adds factory registration for register blocks. UVM encourages registering component and object classes with the factory. While it's not necessary to register *all* classes (eg individual registers), registering...

Support controlling dumpfile and dump enable via plusargs

1

Thanks for taking the time to report this. What would you like added/supported? Several other simulators provide a way to control the dumpfile name and enable status from the simulation-image...